1. Technical Field
The present disclosure relates to the field of integrated circuits. The present disclosure relates more particularly to the field of voltage controlled oscillators implemented in integrated circuits.
2. Description of the Related Art
FIG. 1 is a schematic diagram of an integrated circuit die including a known voltage-controlled oscillator 21. The voltage-controlled oscillator 21 includes a first inverter 24a, a second inverter 24b, and a third inverter 24c connected in series. A PMOS transistor M1 is coupled to respective supply terminals of the first, second, and third inverters 24a-24c. The source terminal of the transistor M1 is coupled to the voltage supply terminal VDD. The gate terminal of the transistor M1 is coupled to the control voltage terminal Vcontrol.
The voltage-controlled oscillator 21 is a ring oscillator. The voltage-controlled oscillator 21 outputs an oscillator signal having a frequency f0 from the output of the inverter 24c. The output of the inverter 24c is supplied to the input of the inverter 24a. In this way the voltage-controlled oscillator 21 receives at its input the output oscillation signal.
Because there are an odd number of inverters, and the inverter 24a receives as its input the output of the inverter 24c, an oscillating signal is generated at the output of the inverter 24c. Because the output of an inverter is the logical “not” of the input, when the input of the inverter 24a is high, the output of the inverter 24a will transition low. Because the output of the inverter 24a is coupled to the input of the inverter 24b, when the output of the inverter 24a transitions low, the output of the inverter 24b will transition high. Because the output of the inverter 24b is the input of the inverter 24c, when the output of the inverter 24b transitions high, the output of the inverter 24c will transition low. Because the output of the inverter 24c is fed back to the input of the inverter 24a, the input of the inverter 24a will transition from a previously high state to the low state of the output of the inverter 24c. When the input of the inverter 24a is low, the output of the inverter 24c will transition high. Thus, an oscillating signal is generated at the output of the inverter 24c. 
Each of the transitions from high to low or low to high at the outputs of the inverters 24a-24c takes a finite amount of time. The period of the oscillator signal is the product of the number of inverters in the ring oscillator 21 multiplied by the time required for an inverter to make a single transition from a low to a high or a high to a low state multiplied by 2 because the period will include both a half on the low state and a half cycle on the high state, the high and the low state together forming one cycle. For example, if the transition time for one of the inverters of the oscillator 21 is 0.1 ns, then the total period of the oscillator signal is 0.6 ns. If the period of the oscillator signal is 0.6 ns, then the frequency of the oscillator signal, which is the inverse of the period of the oscillator signal, is about 1.67 Ghz.
The period of transition between high and low states corresponds to the time it takes for the inherent capacitors (gate-body, gate-source, gate-drain) of a transistor of the inverter to charge or discharge. The time required for the inherent capacitors of the transistor to charge or discharge depends in part on the dimensions of the gate electrode/channel region and the current that drives the inverter.
In the example of FIG. 1, the inverters 24a-24c are driven by a driving current Idrive supplied by the transistor M1. The higher the drive current Idrive, the faster the inverters 24a-24c can transition between the high and low states. The magnitude of the drive current Idrive is dependent on the gate-source voltage of the transistor M1. The voltage at the source of the transistor M1 is fixed at VDD. The gate terminal of the transistor M1 is coupled to a variable voltage source Vcontrol. By adjusting the magnitude of the voltage Vcontrol, the magnitude of the drive current Idrive can be adjusted. Because the output frequency f0 of the oscillator signal is dependent on the drive current Idrive, f0 can be adjusted by adjusting the magnitude of the voltage Vcontrol.
In the oscillator 21 of FIG. 1, to generate very high frequencies the gain of the oscillator becomes very large. For example, if the oscillator 21 has a standard output frequency f0 of about 3 GHz, the gain of the oscillator can go as high as 12 GHz/V. This is because to keep M1 in saturation its size needs to be very large and thus the transconductance, gm, is quite large as well. This is particularly true in oscillators with small supply voltages.
However, the drawback of such a high gain oscillator 21 is that, when implemented in a phase locked loop (PLL), the thermal noise of the resistor present in the loop filter gets multiplied by the square of the gain of the oscillator 21. This creates high phase noise in the output oscillator signal. Such high gain oscillators can make it particularly difficult to get very high performance PLLs with very low jitter. If, in order to reduce the jitter, the size of the resistor in the loop filter is reduced, the size of the capacitor in the loop filter must be increased to make the phase margin acceptable. If the size of the capacitor in the loop filter is increased then a large amount of chip area is consumed.